Chapter 5

Coprocessor

Topical Cross-reference for Coprocessor Instructions................ 146

Interpreting Coprocessor Instructions............................ 148

Syntax............................................... 148

Examples............................................. 148

Clock Speeds.......................................... 148

Instruction Size......................................... 148

Architecture.............................................. 149

Topical Cross-reference for Coprocessor Instructions

Arithmetic

FABS	FADD/FIADD	FADDP
FCHS	FDIV/FIDIV	FDIVP
FDIVR/FIDIVR	FDIVRP	FMUL/FIMUL
FMULP	FPREM	FPREM1^§
FRNDINT	FSCALE	FSQRT
FSUB/FISUB	FSUBP	FSUBR/FISUBR
FSUBRP	FXTRACT

Compare

FCOM/FICOM	FCOMP/FICOMP	FCOMPP
FSTSW/FNSTSW	FTST	FUCOM^§
FUCOMP^§	FUCOMPP^§	FXAM

Load

FLD/FILD/FBLD	FLDCW	FLDENV
FRSTOR	FXCH

Load Constant

FLD1	FLDL2E	FLDL2T
FLDLG2	FLDLN2	FLDPI
FLDZ

Processor Control

FCLEX/FNCLEX	FDECSTP	FDISI/FNDISI*
FENI/FNENI*	FFREE	FINCSTP
FINIT/FNINIT	FLDCW	FNOP
FRSTOR	FSAVE/FNSAVE	FSETPM^_
FSTCW/FNSTCW	FSTENV/FNSTENV	FSTSW/FNSTSW
FWAIT

Store Data

FSAVE/FNSAVE	FST/FIST	FSTCW/FNSTCW
FSTENV/FNSTENV	FSTP/FISTP/FBSTP	FSTSW/FNSTSW

Transcendental

F2XM1	FCOS^§	FPATAN
FPREM	FPREM1^§	FPTAN
FSIN^§	FSINCOS^§	FYL2P1
FYL2X

* 8087 only † 80287 only. § 80387–80486 only.

Interpreting Coprocessor Instructions

This section provides an alphabetical reference to instructions of the 8087, 80287, and 80387 coprocessors. The format is the same as the processor instructions except that encodings are not provided. Differences are noted in the following.

The 80486 has the coprocessor built in. This one chip executes all the instructions listed in the previous section and this section.

Syntax

Syntaxes in Column 1 use the following abbreviations for operand types:

Syntax	Operand
reg	A coprocessor stack register
memreal	A direct or indirect memory operand storing a real number
memint	A direct or indirect memory operand storing a binary integer
membcd	A direct or indirect memory operand storing a BCD number

Examples

The position of the examples in Column 2 is not related to the clock speeds in Column 3.

Clock Speeds

Column 3 shows the clock speeds for each processor. Sometimes an instruction may have more than one possible clock speed. The following abbreviations are used to specify variations:

Abbreviation	Description
EA	Effective address. This applies only to the 8087. See the Processor Section, “Timings on the 8088 and 8086 Processors,” for an explanation of effective address timings.
s,l,t	Short real, long real, and 10-byte temporary real.
w,d,q	Word, doubleword, and quadword binary integer.
to, fr	To or from stack top. On the 80387 and 80486, the to clocks represent timings when ST is the destination. The fr clocks represent timings when ST is the source.

Instruction Size

The instruction size is always 2 bytes for instructions that do not access memory. For instructions that do access memory, the size is 4 bytes on the 8087 and 80287. On the 80387 and 80486, the size for instructions that access memory is 4 bytes in 16-bit mode, or 6 bytes in 32-bit mode.

On the 8087, each instruction must be preceded by the WAIT (also called FWAIT) instruction, thereby increasing the instruction’s size by 1 byte. The assembler inserts WAIT automatically by default, or with the .8087 directive.

Architecture

The 8087, 80287, and 80387 coprocessors, along with the 80486, have several common elements of architecture. All have a register stack made up of eight 80-bit data registers. These can contain floating-point numbers in the temporary real format. The coprocessors also have 14 bytes of control registers. Figure 5.1 shows the format of registers.

Fig. 5 . 1 Coprocessor Registers

The most important control registers are the control word and the status word. Figure 5.2 shows the format of these registers.

Fig. 5 . 2 Control Word and Status Word

F2XM1 2^X–1

Calculates Y = 2^X – 1. X is taken from ST. The result, Y, is returned in ST. X must be in the range 0 X 0.5 on the 8087/287, or in the range –1.0 X +1.0 on the 80387–80486.

Syntax	Examples	CPU	Clock Cycles
F2XM1	f2xm1	87 287 387 486	310–630 310–630 211–476 140––279

FABS Absolute Value

Converts the element in ST to its absolute value.

Syntax	Examples	CPU	Clock Cycles
FABS	fabs	87 287 387 486	10–17 10–17 22 3

FADD/FADDP/FIADD Add

Adds the source to the destination and returns the sum in the destination. If two register operands are specified, one must be ST. If a memory operand is specified, the sum replaces the value in ST. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified, ST is added to ST(1) and the stack is popped, returning the sum in ST. For FADDP, the source must be ST; the sum is returned in the destination and ST is popped.

Syntax	Examples	CPU	Clock Cycles
FADD [[reg,reg]]	fadd st,st(2) fadd st(5),st fadd	87 287 387 486	70–100 70–100 to=23–31, fr=26–34 8–20
FADDP reg,ST	faddp st(6),st	87 287 387 486	75–105 75–105 23–31 8–20
FADD memreal	fadd QWORD PTR [bx] fadd shortreal	87 287 387 486	(s=90–120,s=95–125)+EA s=90–120,l=95–125 s=24–32,l=29–37 8–20
FIADD memint	fiadd int16 fiadd warray[di] fiadd double	87 287 387 486	(w=102–137,d=108 –143)+EA w=102–137,d=108 –143 w=71–85,d=57–72 w=20–35,d=19–32

FBLD Load BCD

See FLD.

FBSTP Store BCD and Pop

See FST.

FCHS Change Sign

Reverses the sign of the value in ST.

Syntax	Examples	CPU	Clock Cycles
FCHS	fchs	87 287 387 486	10–17 10–17 24–25 6

FCLEX/FNCLEX Clear Exceptions

Clears all exception flags, the busy flag, and bit 7 in the status word. Bit 7 is the interrupt-request flag on the 8087, and the error-status flag on the 80287, 80387, and 80486. The instruction has wait and no-wait versions.

Syntax	Examples	CPU	Clock Cycles*
FCLEX FNCLEX	fclex	87 287 387 486	2–8 2–8 11 7

* These timings reflect the no-wait version of the instruction. The wait version may take additional clock cycles.

FCOM/FCOMP/FCOMPP/FICOM/FICOMP Compare

Compares the specified source operand to ST and sets the condition codes of the status word according to the result. The instruction subtracts the source operand from ST without changing either operand. Memory operands can be 32- or 64-bit real numbers or 16- or 32-bit integers. If no operand is specified or if two pops are specified, ST is compared to ST(1) and the stack is popped. If one pop is specified with an operand, the operand is compared to ST. If one of the operands is a NAN, an invalid-operation exception occurs (see FUCOM for an alternative method of comparing on the 80387–80486).

Syntax	Examples	CPU	Clock Cycles
FCOM [[reg]]	fcom st(2) fcom	87 287 387 486	40–50 40–50 24 4
FCOMP [[reg]]	fcomp st(7) fcomp	87 287 387 486	42–52 42–52 26 4
FCOMPP	fcompp	87 287 387 486	45–55 45–55 26 5
FCOM memreal	fcom shortreals[di] fcom longreal	87 287 387 486	(s=60–70,l=65–75)+EA s=60–70,l=65–75 s=26,l=31 4
FCOMP memreal	fcomp longreal fcomp shorts[di]	87 287 387 486	(s=63–73,l=67–77)+EA s=63–73,l=67–77 s=26,l=31 4
FICOM memint	ficom double ficom warray[di]	87 287 387 486	(w=72–86,d=78–91)+EA w=72–86,d=78–91 w=71–75,d=56–63 w=16–20,d=15–17
FICOMP memint	ficomp WORD PTR [bp+6] ficomp darray[di]	87 287 387 486	(w=74–88,d=80–93)+EA w=74–88,d=80–93 w=71–75,d=56–63 w=16–20,d=15–17

Condition Codes for FCOM

C3	C2	C1	C0	Meaning
0	0	?	0	ST > source <